set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets level0_i/ulp/ulp_ucs/inst/clkwiz_kernel2/inst/CLK_CORE_DRP_I/clk_inst/clk_out1]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets level0_i/ulp/ulp_ucs/inst/shell_utils_clock_throttling_kernel2/U0/Clk_Out]
#using 19.2 daily latest hier update to the following 
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets level0_i/ulp/ulp_ucs/inst/clock_throttling_kernel2/U0/Clk_Out]
#We do not need PR for SLR0 and SLR1
set_property SNAPPING_MODE NESTED [get_pblocks pblock_dynamic_SLR0]
set_property SNAPPING_MODE NESTED [get_pblocks pblock_dynamic_SLR1]

#remove clock root
#set_property USER_CLOCK_ROOT X3Y1 [get_nets level0_i/ulp/ulp_ucs/inst/shell_utils_clock_throttling_kernel/U0/Clk_Out]
#set_property USER_CLOCK_ROOT X3Y1 [get_nets level0_i/ulp/ulp_ucs/inst/shell_utils_clock_throttling_kernel2/U0/Clk_Out]

create_generated_clock -name ACLK0 [get_pins "level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/dpu_clock_gen_inst/u_dpu_mmcm/inst/mmcme4_adv_inst/CLKOUT1"]
create_generated_clock -name ACLK_DR0 [get_pins "level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/dpu_clock_gen_inst/u_dpu_mmcm/inst/mmcme4_adv_inst/CLKOUT0"]
create_generated_clock -name ACLK_REG0 [get_pins "level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/dpu_clock_gen_inst/u_dpu_mmcm/inst/mmcme4_adv_inst/CLKOUT2"]

#set_multicycle_path -setup 2 -from [get_pins " \
#level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_clock_gen_0/inst/RESET_REG_CONTROL[3].reset_reg_counter_reg[3]*/C\
#"]
#set_multicycle_path -hold  1 -from [get_pins " \
#level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_clock_gen_0/inst/RESET_REG_CONTROL[3].reset_reg_counter_reg[3]*/C\
#"]

#set_property CLOCK_DELAY_GROUP CGRP_SLR0 [get_nets "level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_B level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C_DR level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_F level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_LI level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_LW level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_M level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_S level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_SW"]
set_property CLOCK_DELAY_GROUP CGRP_SLR0 [get_nets "level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_B level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C_DR level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_CS level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_OUT level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_LI level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_LW level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_M level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_S level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_SW"]
#set_property CLOCK_DELAY_GROUP CGRP_SLR0 [get_nets "level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C_DR level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_CS level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_OUT"]
#set_property CLOCK_DELAY_GROUP CGRP_SLR0_ROOT [get_nets "level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/ACLK_DR"]
add_cells_to_pblock [get_pblocks pblock_dynamic_SLR0] [get_cells " \
level0_i/ulp/dpu_0/inst/v3e_bd_i/axi_clock_converter_0 \
level0_i/ulp/dpu_0/inst/v3e_bd_i/axi_clock_converter_1 \
level0_i/ulp/dpu_0/inst/v3e_bd_i/axi_clock_converter_2 \
level0_i/ulp/dpu_0/inst/v3e_bd_i/axi_clock_converter_I0 \
level0_i/ulp/dpu_0/inst/v3e_bd_i/axi_clock_converter_W0 \
level0_i/ulp/dpu_0/inst/v3e_bd_i/axi_clock_converter_W1 \
level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_clock_gen_0 \
level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0 \
"]

add_cells_to_pblock [get_pblocks pblock_dynamic_SLR0] [get_cells " \
level0_i/ulp/dpu_0/inst/v3e_bd_i/axi_clock_converter_csr \
"]

set_property LOC DSP48E2_X18Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y74 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y82 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y66 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X10Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X10Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X10Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X10Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]

#Locate IMG bank in SLR1






#1M weight loc
#set_property LOC URAM288_X3Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[0].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y1 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[0].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y2 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[1].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y3 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[1].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y4 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[2].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y5 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[2].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y6 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[3].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y7 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[3].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[4].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y9 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[4].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y10 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[5].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y11 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[5].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y12 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[6].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y13 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[6].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y14 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[7].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y15 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[7].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[8].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y17 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[8].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y18 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[9].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y19 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[9].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y20 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[10].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y21 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[10].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y22 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[11].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y23 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[11].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[12].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y25 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[12].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y26 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[13].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y27 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[13].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y28 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[14].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y29 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[14].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y30 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[15].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y31 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[15].u_ram/ram_reg_uram_1]
#8M weight loc
#set_property LOC URAM288_X0Y4 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X0Y5 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X0Y6 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X0Y7 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X0Y12 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X0Y13 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X0Y14 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X0Y15 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X0Y20 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X0Y21 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X0Y22 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X0Y23 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X0Y28 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X0Y29 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X0Y30 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X0Y31 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X0Y36 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X0Y37 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X0Y38 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X0Y39 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X0Y44 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X0Y45 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X0Y46 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X0Y47 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X0Y52 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X0Y53 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X0Y54 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X0Y55 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X0Y60 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X0Y61 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X0Y62 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X0Y63 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X1Y4 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X1Y5 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X1Y6 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X1Y7 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X1Y12 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X1Y13 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X1Y14 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X1Y15 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X1Y20 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X1Y21 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X1Y22 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X1Y23 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X1Y28 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X1Y29 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X1Y30 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X1Y31 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X1Y36 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X1Y37 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X1Y38 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X1Y39 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X1Y44 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X1Y45 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X1Y46 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X1Y47 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X1Y52 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X1Y53 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X1Y54 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X1Y55 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X1Y60 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X1Y61 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X1Y62 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X1Y63 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X2Y4 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X2Y5 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X2Y6 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X2Y7 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X2Y12 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X2Y13 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X2Y14 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X2Y15 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X2Y20 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X2Y21 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X2Y22 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X2Y23 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X2Y28 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X2Y29 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X2Y30 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X2Y31 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X2Y36 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X2Y37 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X2Y38 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X2Y39 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X2Y44 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X2Y45 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X2Y46 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X2Y47 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X2Y52 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X2Y53 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X2Y54 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X2Y55 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X2Y60 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X2Y61 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X2Y62 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X2Y63 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X3Y4 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y5 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y6 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X3Y7 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X3Y12 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X3Y13 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X3Y14 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X3Y15 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X3Y20 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y21 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y22 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X3Y23 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X3Y28 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X3Y29 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X3Y30 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X3Y31 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X3Y36 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y37 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y38 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X3Y39 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X3Y44 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X3Y45 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X3Y46 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X3Y47 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X3Y52 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y53 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y54 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X3Y55 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X3Y60 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X3Y61 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X3Y62 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X3Y63 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X0Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X0Y1 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X0Y2 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X0Y3 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X0Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X0Y9 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X0Y10 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X0Y11 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X0Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X0Y17 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X0Y18 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X0Y19 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X0Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X0Y25 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X0Y26 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X0Y27 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X0Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X0Y33 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X0Y34 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X0Y35 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X0Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X0Y41 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X0Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X0Y43 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X0Y48 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X0Y49 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X0Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X0Y51 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X0Y56 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X0Y57 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X0Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X0Y59 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X1Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X1Y1 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X1Y2 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X1Y3 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X1Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X1Y9 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X1Y10 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X1Y11 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X1Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X1Y17 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X1Y18 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X1Y19 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X1Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X1Y25 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X1Y26 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X1Y27 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X1Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X1Y33 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X1Y34 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X1Y35 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X1Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X1Y41 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X1Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X1Y43 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X1Y48 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X1Y49 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X1Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X1Y51 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X1Y56 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X1Y57 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X1Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X1Y59 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X2Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X2Y1 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X2Y2 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X2Y3 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X2Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X2Y9 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X2Y10 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X2Y11 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X2Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X2Y17 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X2Y18 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X2Y19 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X2Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X2Y25 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X2Y26 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X2Y27 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X2Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X2Y33 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X2Y34 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X2Y35 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X2Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X2Y41 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X2Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X2Y43 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X2Y48 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X2Y49 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X2Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X2Y51 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X2Y56 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X2Y57 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X2Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X2Y59 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X3Y0 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y1 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y2 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X3Y3 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X3Y8 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X3Y9 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X3Y10 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X3Y11 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X3Y16 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y17 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y18 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X3Y19 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X3Y24 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X3Y25 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X3Y26 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X3Y27 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X3Y32 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y33 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y34 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X3Y35 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X3Y40 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X3Y41 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X3Y42 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X3Y43 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_7]
#set_property LOC URAM288_X3Y48 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y49 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y50 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_2]
#set_property LOC URAM288_X3Y51 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_3]
#set_property LOC URAM288_X3Y56 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_4]
#set_property LOC URAM288_X3Y57 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_5]
#set_property LOC URAM288_X3Y58 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_6]
#set_property LOC URAM288_X3Y59 [get_cells level0_i/ulp/dpu_0/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_7]
#
#
create_generated_clock -name ACLK1 [get_pins "level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/dpu_clock_gen_inst/u_dpu_mmcm/inst/mmcme4_adv_inst/CLKOUT1"]
create_generated_clock -name ACLK_DR1 [get_pins "level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/dpu_clock_gen_inst/u_dpu_mmcm/inst/mmcme4_adv_inst/CLKOUT0"]
create_generated_clock -name ACLK_REG1 [get_pins "level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/dpu_clock_gen_inst/u_dpu_mmcm/inst/mmcme4_adv_inst/CLKOUT2"]

#set_multicycle_path -setup 2 -from [get_pins " \
#level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_clock_gen_0/inst/RESET_REG_CONTROL[3].reset_reg_counter_reg[3]*/C\
#"]
#set_multicycle_path -hold  1 -from [get_pins " \
#level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_clock_gen_0/inst/RESET_REG_CONTROL[3].reset_reg_counter_reg[3]*/C\
#"]

#set_property CLOCK_DELAY_GROUP CGRP_SLR1 [get_nets "level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_B level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C_DR level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_F level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_LI level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_LW level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_M level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_S level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_SW"]
set_property CLOCK_DELAY_GROUP CGRP_SLR1 [get_nets "level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_B level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C_DR level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_CS level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_OUT level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_LI level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_LW level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_M level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_S level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_SW"]
#set_property CLOCK_DELAY_GROUP CGRP_SLR1 [get_nets "level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_C_DR level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_CS level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_OUT"]
#set_property CLOCK_DELAY_GROUP CGRP_SLR1_ROOT [get_nets "level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/ACLK_DR"]
add_cells_to_pblock [get_pblocks pblock_dynamic_SLR1] [get_cells " \
level0_i/ulp/dpu_1/inst/v3e_bd_i/axi_clock_converter_0 \
level0_i/ulp/dpu_1/inst/v3e_bd_i/axi_clock_converter_1 \
level0_i/ulp/dpu_1/inst/v3e_bd_i/axi_clock_converter_2 \
level0_i/ulp/dpu_1/inst/v3e_bd_i/axi_clock_converter_I0 \
level0_i/ulp/dpu_1/inst/v3e_bd_i/axi_clock_converter_W0 \
level0_i/ulp/dpu_1/inst/v3e_bd_i/axi_clock_converter_W1 \
level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_clock_gen_0 \
level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0 \
"]

add_cells_to_pblock [get_pblocks pblock_dynamic_SLR0] [get_cells " \
level0_i/ulp/dpu_1/inst/v3e_bd_i/axi_clock_converter_csr \
"]

#create_pblock pblock_dynamic_SLR0_dpu_1
#add_cells_to_pblock [get_pblocks pblock_dynamic_SLR0_dpu_1] [get_cells " \
#level0_i/ulp/hmss_0/inst/path_20/interconnect*/inst/s00_entry_pipeline \
#level0_i/ulp/hmss_0/inst/path_1/interconnect*/inst/s00_entry_pipeline \
#level0_i/ulp/hmss_0/inst/path_17/interconnect*/inst/s00_entry_pipeline \
#level0_i/ulp/hmss_0/inst/path_19/interconnect*/inst/s00_entry_pipeline \
#level0_i/ulp/hmss_0/inst/path_2/interconnect*/inst/s00_entry_pipeline \
#level0_i/ulp/hmss_0/inst/path_4/interconnect*/inst/s00_entry_pipeline \
#level0_i/ulp/hmss_0/inst/path_7/interconnect*/inst/s00_entry_pipeline \
#level0_i/ulp/hmss_0/inst/path_8/interconnect*/inst/s00_entry_pipeline \
#"]
#resize_pblock [get_pblocks pblock_dynamic_SLR0_dpu_1] -add {CLOCKREGION_X0Y3:CLOCKREGION_X6Y3}
set_property LOC DSP48E2_X18Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y164 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y172 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y132 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y140 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y148 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y156 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_2/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X16Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X17Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X18Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X19Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X20Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X21Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X22Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X23Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X24Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X25Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X26Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X27Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X28Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_1/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X0Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[0].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X1Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[2].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X2Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X3Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[4].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X4Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[6].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X5Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[8].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X6Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X7Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[10].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X8Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[12].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[0].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X9Y130 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[1].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X10Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X10Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[2].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X10Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[0].GenMidCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
set_property LOC DSP48E2_X10Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/gen_dpu.m_dpu_0/m_conv_top/inst_pea/GenOcp[14].u_pe/GenMultCvb.GenMultech[1].GenLastCvb.u_conv_block/GenConvChain[0].GenConvPair[3].Gen8x8.GenMultDsp.GenFirDsp.u_dsp_unit_fir/DSP48E2_gen.DSP48E2_inst]
#===================================================================
#Locate IMG bank in SLR1



#1MB weight loc
#set_property LOC URAM288_X3Y64 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[0].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y65 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[0].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y66 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[1].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y67 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[1].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y68 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[2].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y69 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[2].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y70 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[3].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y71 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[3].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y72 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[4].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y73 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[4].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y74 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[5].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y75 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[5].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y76 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[6].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y77 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[6].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y78 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[7].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y79 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[7].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y80 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[8].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y81 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[8].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y82 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[9].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y83 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[9].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y84 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[10].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y85 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[10].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y86 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[11].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y87 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[11].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y88 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[12].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y89 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[12].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[13].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y91 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[13].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y92 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[14].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y93 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[14].u_ram/ram_reg_uram_1]
#set_property LOC URAM288_X3Y94 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[15].u_ram/ram_reg_uram_0]
#set_property LOC URAM288_X3Y95 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/genblk1.u_weights_buf/unpack_ram_addr[15].u_ram/ram_reg_uram_1]
#8MB weight loc
#TEMP set_property LOC URAM288_X0Y68 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X0Y69 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X0Y70 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X0Y71 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X0Y76 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X0Y77 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X0Y78 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X0Y79 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[0].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X0Y84 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X0Y85 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X0Y86 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X0Y87 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X0Y92 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X0Y93 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X0Y94 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X0Y95 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[1].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X0Y100 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X0Y101 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X0Y102 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X0Y103 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X0Y108 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X0Y109 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X0Y110 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X0Y111 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[2].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X0Y116 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X0Y117 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X0Y118 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X0Y119 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X0Y124 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X0Y125 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X0Y126 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X0Y127 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[3].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X1Y68 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X1Y69 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X1Y70 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X1Y71 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X1Y76 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X1Y77 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X1Y78 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X1Y79 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[4].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X1Y84 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X1Y85 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X1Y86 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X1Y87 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X1Y92 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X1Y93 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X1Y94 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X1Y95 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[5].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X1Y100 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X1Y101 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X1Y102 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X1Y103 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X1Y108 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X1Y109 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X1Y110 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X1Y111 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[6].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X1Y116 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X1Y117 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X1Y118 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X1Y119 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X1Y124 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X1Y125 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X1Y126 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X1Y127 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[7].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X2Y68 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X2Y69 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X2Y70 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X2Y71 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X2Y76 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X2Y77 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X2Y78 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X2Y79 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[8].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X2Y84 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X2Y85 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X2Y86 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X2Y87 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X2Y92 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X2Y93 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X2Y94 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X2Y95 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[9].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X2Y100 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X2Y101 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X2Y102 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X2Y103 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X2Y108 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X2Y109 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X2Y110 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X2Y111 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[10].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X2Y116 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X2Y117 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X2Y118 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X2Y119 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X2Y124 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X2Y125 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X2Y126 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X2Y127 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[11].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X3Y68 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X3Y69 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X3Y70 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X3Y71 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X3Y76 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X3Y77 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X3Y78 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X3Y79 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[12].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X3Y84 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X3Y85 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X3Y86 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X3Y87 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X3Y92 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X3Y93 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X3Y94 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X3Y95 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[13].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X3Y100 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X3Y101 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X3Y102 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X3Y103 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X3Y108 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X3Y109 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X3Y110 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X3Y111 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[14].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X3Y116 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X3Y117 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X3Y118 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X3Y119 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X3Y124 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X3Y125 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X3Y126 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X3Y127 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_h/unpack_ram_addr[15].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X0Y64 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X0Y65 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X0Y66 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X0Y67 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X0Y72 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X0Y73 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X0Y74 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X0Y75 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[0].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X0Y80 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X0Y81 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X0Y82 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X0Y83 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X0Y88 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X0Y89 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X0Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X0Y91 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[1].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X0Y96 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X0Y97 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X0Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X0Y99 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X0Y104 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X0Y105 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X0Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X0Y107 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[2].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X0Y112 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X0Y113 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X0Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X0Y115 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X0Y120 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X0Y121 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X0Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X0Y123 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[3].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X1Y64 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X1Y65 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X1Y66 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X1Y67 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X1Y72 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X1Y73 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X1Y74 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X1Y75 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[4].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X1Y80 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X1Y81 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X1Y82 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X1Y83 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X1Y88 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X1Y89 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X1Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X1Y91 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[5].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X1Y96 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X1Y97 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X1Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X1Y99 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X1Y104 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X1Y105 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X1Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X1Y107 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[6].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X1Y112 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X1Y113 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X1Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X1Y115 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X1Y120 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X1Y121 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X1Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X1Y123 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[7].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X2Y64 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X2Y65 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X2Y66 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X2Y67 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X2Y72 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X2Y73 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X2Y74 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X2Y75 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[8].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X2Y80 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X2Y81 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X2Y82 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X2Y83 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X2Y88 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X2Y89 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X2Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X2Y91 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[9].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X2Y96 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X2Y97 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X2Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X2Y99 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X2Y104 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X2Y105 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X2Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X2Y107 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[10].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X2Y112 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X2Y113 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X2Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X2Y115 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X2Y120 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X2Y121 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X2Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X2Y123 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[11].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X3Y64 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X3Y65 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X3Y66 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X3Y67 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X3Y72 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X3Y73 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X3Y74 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X3Y75 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[12].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X3Y80 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X3Y81 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X3Y82 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X3Y83 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X3Y88 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X3Y89 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X3Y90 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X3Y91 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[13].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X3Y96 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X3Y97 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X3Y98 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X3Y99 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X3Y104 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X3Y105 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X3Y106 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X3Y107 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[14].u_ram/ram_reg_uram_7]
#TEMP set_property LOC URAM288_X3Y112 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_0]
#TEMP set_property LOC URAM288_X3Y113 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_1]
#TEMP set_property LOC URAM288_X3Y114 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_2]
#TEMP set_property LOC URAM288_X3Y115 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_3]
#TEMP set_property LOC URAM288_X3Y120 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_4]
#TEMP set_property LOC URAM288_X3Y121 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_5]
#TEMP set_property LOC URAM288_X3Y122 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_6]
#TEMP set_property LOC URAM288_X3Y123 [get_cells level0_i/ulp/dpu_1/inst/v3e_bd_i/dpu_top_0/inst/m_share_wt_top/u_share_wt_bank/u_weights_buf_l/unpack_ram_addr[15].u_ram/ram_reg_uram_7]
